1. Field of the Invention
The present invention relates to a memory backup control apparatus and method for controlling cutoff and recovery of a power supply with respect to a memory, which holds data, while selectively using a main power supply and backup power supply.
2. Related Background Art
In general, when data is backed up in a system that requires a large-capacity memory, a memory backup circuit uses a volatile memory such as a DRAM (dynamic random access memory) or the like as a memory element. A memory backup control apparatus may have a refresh circuit for restoring (rewriting) data to hold the data in the DRAM, a selector for switching between a system operation mode and backup mode upon refreshing the DRAM, a power supply voltage monitoring circuit for monitoring the power supply voltage of the system, and a backup power supply circuit for obtaining a voltage equal to the power supply voltage of the system.
In such arrangement, conventionally, transfer to backup operation is done as follows. That is, upon detecting a power supply voltage drop or decrease resulting from, e.g., power failure by the power supply voltage monitoring circuit, a reset signal is output to the system. At the same time, the selector is switched to the refresh circuit that operates in only the backup mode and the backup refresh circuit is started up. Alternatively, a CBR (CAS before RAS) timing is generated based on a RAS (row address strobe) signal and CAS (column address strobe) signal to start up self refresh of the DRAM. In this way, data is backed up.
Upon recovery of the power supply, after recovery of the power supply voltage is detected by the power supply voltage monitoring circuit, the system reset is canceled and, at the same time, the DRAM refresh circuit is switched from the backup side to the system side by the selector.
DRAM control upon transfer to or recovery from the backup control is done using a hardware timing asynchronous with the system clock.
Since the conventional memory backup control apparatus has the aforementioned arrangement, fast memory control is limited in a system that requires a large-capacity memory. Also, the CBR timing of the RAS and CAS signals must be generated by hardware or a gate array, and simple, fast control/processing cannot be implemented.